- 地点
- 圣何塞,美国
- 工作方式
- 混合办公
- 类型
- 全职
- 资历
- senior
- 部门
- 系统设计
职责
- 负责 Groq AI 加速器硬件底层固件的端到端开发。
- 作为产品全线(引导加载程序、驱动程序、实时操作系统、应用层服务)固件的主要技术权威,负责提供愿景、制定标准,并在性能、功耗、安全性和可维护性之间做出权衡决策。
- 通过定期开展设计评审、结对编程和“固件午餐会”技术交流,提升团队实力。指导初级和中级工程师;制定晋升路径,帮助工程师晋升为高级工程师或首席工程师。
- 将产品需求文档 (PRD) 翻译成详细的固件规范、架构图和接口合同。
- 定义可在多个 Groq 产品中利用的模块化、可重用的固件框架。
- 利用深厚的嵌入式 Linux 和 RTOS 专业知识,包括创建和维护设备树 blob,以描述固件-硬件配置,用于自定义板集成。
- 设计并记录固件-硬件接口,确保与设备树和 RTOS 层无缝集成。
- 主导对延迟关键路径(例如,LPU DMA、中断延迟、电源状态转换)的系统性分析、优化和验证。实施稳健的错误处理、看门狗和安全机制,以确保生产环境中 99.99% 以上的正常运行时间。
- 与硬件、芯片、系统软件和人工智能软件团队紧密合作,共同设计接口(PCIe、DDR、高速 SerDes、I²C、SPI 等)。推动集成测试策略,并快速解决跨领域缺陷。
- 识别并实施流程改进(固件持续集成/持续交付流水线、自动化回归测试、静态分析、代码审查标准)。倡导以数据驱动决策为导向的文化,从而带来可衡量的质量提升。
- 负责新 LPU 芯片的启动工作,包括引导加载程序开发、早期外设启动和芯片后验证。在实验室中使用示波器、逻辑分析仪、JTAG/SWD 和系统内跟踪工具进行实际调试。
- 集成安全启动、固件加密、认证和其他安全原语。支持产品认证(例如 FCC、CE)和上市准备活动。
必备要求
- 计算机工程、电气工程、计算机科学或相关领域的理学士学位。
- 在复杂、高性能 SoC/ASIC 平台(最好是 AI/ML 加速器)上拥有 10 年以上的专业固件开发经验。
- 精通 C/C++(C-11 或更高版本)、汇编语言和底层硬件交互(内存映射 I/O、中断处理、DMA、引导加载程序设计)。
- 拥有实时操作系统(FreeRTOS、Zephyr、VxWorks、ThreadX)和/或裸机固件在延迟关键型工作负载方面的丰富经验。
- 熟练掌握高速接口(PCIe Gen3/4、DDR4/5、SerDes、以太网)和低速总线(SPI、I²C、UART、CAN)。
优先条件
- AI/ML 固件 – 之前从事 AI/ML 推理引擎、张量加速器或类似工作负载的固件开发工作。
- 数据中心经验 – 了解服务器级电源、冷却和可靠性要求。
Responsibilities
- Own end-to-end development of low-level firmware for Groq AI accelerator hardware.
- Serve as the primary technical authority for firmware across the product line (bootloaders, drivers, RTOS, application-layer services), providing vision, setting standards, and making trade-off decisions among performance, power, security, and maintainability.
- Empower the team through regular design reviews, pair programming, and "firmware lunch" technical exchanges. Mentor junior and mid-level engineers; define promotion paths to help engineers advance to senior or principal engineer.
- Translate product requirements documents (PRDs) into detailed firmware specifications, architecture diagrams, and interface contracts.
- Define modular, reusable firmware frameworks leveraged across multiple Groq products.
- Leverage deep embedded Linux and RTOS expertise, including creating and maintaining device tree blobs to describe firmware-hardware configurations for custom board integration.
- Design and document firmware-hardware interfaces, ensuring seamless integration with device tree and RTOS layers.
- Lead systematic analysis, optimization, and validation of latency-critical paths (e.g., LPU DMA, interrupt latency, power state transitions). Implement robust error handling, watchdogs, and safety mechanisms to ensure >99.99% uptime in production.
- Collaborate closely with hardware, chip, system software, and AI software teams to co-design interfaces (PCIe, DDR, high-speed SerDes, I²C, SPI, etc.). Drive integration test strategies and quickly resolve cross-domain defects.
- Identify and implement process improvements (firmware CI/CD pipelines, automated regression testing, static analysis, code review standards). Advocate a data-driven decision-making culture that delivers measurable quality improvements.
- Lead bring-up and debugging of new LPU chips, including bootloader development, early peripheral bring-up, and post-silicon validation. Perform hands-on debugging in the lab using oscilloscopes, logic analyzers, JTAG/SWD, and in-system trace tools.
- Integrate secure boot, firmware encryption, authentication, and other security primitives. Support product certification (e.g., FCC, CE) and launch readiness activities.
Must Have
- BS in Computer Engineering, Electrical Engineering, Computer Science, or related field.
- 10+ years of professional firmware development experience on complex, high-performance SoC/ASIC platforms (preferably AI/ML accelerators).
- Proficiency in C/C++ (C-11 or later), assembly language, and low-level hardware interaction (memory-mapped I/O, interrupt handling, DMA, bootloader design).
- Extensive experience with real-time operating systems (FreeRTOS, Zephyr, VxWorks, ThreadX) and/or bare-metal firmware for latency-critical workloads.
- Strong hands-on experience with high-speed interfaces (PCIe Gen3/4, DDR4/5, SerDes, Ethernet) and low-speed buses (SPI, I²C, UART, CAN).
Preferred
- AI/ML firmware – prior firmware development for AI/ML inference engines, tensor accelerators, or similar workloads.
- Data center experience – understanding of server-level power, cooling, and reliability requirements.
公司简介
Groq 提供快速高效的 AI 推理。我们基于 LPU 的系统为 GroqCloud™ 提供强大支持,为企业和开发者带来所需的速度和规模。从湾区起步,到如今不断拓展的全球业务,我们始终致力于让高性能 AI 计算更加普及和经济实惠。当实时 AI 触手可及,一切皆有可能。快速构建。